Thermo-mechanical behavior of vias in HDI structures

American Society of Mechanical Engineers, EEP

Volumn 19, Issue 2, 1997, Pages 1305-1310

  Dunne, Rajiv C ^a   Smith, Kyle ^a   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 5844401360     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (6)

1. Akhavain, M. and P. McCarty, 1992, "State of Stress in Multilayer Ceramic Packages," ASME Advances in Electronic Packaging, pp. 509-513.
2. Cifuentes, A. O. and I. A. Shareef, 1992, "Modeling of Multilevel Structures: A General Method of Analyzing Stress Evolution during Processing," IEEE Transactions on Semiconductor Manufacturing, Vol. 5, No. 2, pp. 128-137.
3. Dunne, R. C. and Sitaraman, S. K., "Warpage and Stress-Strain Distribution in a Sandwich Substrate with Integrated Passives", 8th Symposium on Mechanics of Surface Mount Assemblies, 96-WA/EEP-6, ASME International Mechanical Engineering Congress, Atlanta, Nov. 1996.
4. Isobe, A., Shinohara, M., Hiraki, M., and Hoshino, A., "Via Hole Failure Study," NEC Research & Development, Vol. 34, No. 1, (1993).
5. Prabhu, A.S., Barker, D. B., and M. G. Pecht, 1995,"A ThermoMechanical Fatigue Analysis of High Density Interconnect Vias," ASME Advances in Electronic Packaging, Vol. 10-1, pp. 187-216.
6. Wu, S.W., Yeh, C-P, Hu, K. X. and K. Wyatt, 1995, "Process Modeling for MultiChip Module Thin Film Interconnects," ASME Journal of Cooling and Thermal Design of Electronic Systems, HTD-Vol. 319/EEP-Vol. 15, pp. 175-179.