Correlation of flip chip underfill process parameters and material properties with in-process stress generation

Proceedings - Electronic Components and Technology Conference

Volumn Part F133492, Issue , 1998, Pages 838-847

  Palaniappan, P ^a   Selman, P J ^a   Baldwin, D ^a   Wu, Jaili ^b   Wong, C P ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSEMBLY; CHIP SCALE PACKAGES; CURING; DISSIMILAR MATERIALS; FIBER OPTIC SENSORS; FLIP CHIP DEVICES; GLASS TRANSITION; NETWORK COMPONENTS; RELIABILITY; STRESSES; SUBSTRATES; THERMAL EXPANSION; PRINTED CIRCUIT BOARDS; STRESS ANALYSIS;

EFFECT OF ENCAPSULATION; FLIP CHIP ASSEMBLIES; IN-SITU STRESS MEASUREMENT; INTERCONNECTION TECHNIQUE; MECHANICAL INTEGRITY; PERFORMANCE AND RELIABILITIES; RELIABILITY PERFORMANCE; SANDIA NATIONAL LABORATORIES;

INTEGRATED CIRCUIT INTERCONNECTS; ELECTRONICS PACKAGING;

STORAGE MODULUS;

EID: 0031628854     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.1998.678805     Document Type: Conference Paper

References (12)

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