메뉴 건너뛰기




Volumn , Issue , 1998, Pages 402-407

A statistical performance simulation methodology for VLSI circuits

Author keywords

[No Author keywords available]

Indexed keywords

INTELLIGENT SYSTEMS; MONTE CARLO METHODS; TIMING CIRCUITS; VLSI CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; STATISTICAL METHODS;

EID: 0031623458     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277153     Document Type: Conference Paper
Times cited : (9)

References (14)
  • 2
    • 0028480268 scopus 로고
    • Relating statistical MOSFET model parameter variabilities to IC manufacturing process fluctuations enabling realistic worst case design
    • August
    • J. Power, B. Donnellan, A. Mathewson, W. Lane, "Relating Statistical MOSFET Model Parameter Variabilities to IC Manufacturing Process Fluctuations Enabling Realistic Worst Case Design", IEEE Trans. Semicon. Manuf., August 1994, pp. 306-318.
    • (1994) IEEE Trans. Semicon. Manuf. , pp. 306-318
    • Power, J.1    Donnellan, B.2    Mathewson, A.3    Lane, W.4
  • 3
    • 0030408583 scopus 로고    scopus 로고
    • Hierarchical statistical characterization of mixed-signal circuits using behavior modeling
    • E. Felt, S. Zanella, G. Guardiani, A. Sangiovanni-Vincentelli, "Hierarchical Statistical Characterization of Mixed-Signal Circuits Using Behavior Modeling, " 1996 Proc. Of IC-CAD, pp. 374-380.
    • (1996) Proc. of IC-CAD , pp. 374-380
    • Felt, E.1    Zanella, S.2    Guardiani, G.3    Sangiovanni-Vincentelli, A.4
  • 4
    • 0029218233 scopus 로고
    • Efficient Worst Case Analysis of Integrated Circuits
    • A. N. Lokanathan, J. B. Brockman, "Efficient Worst Case Analysis of Integrated Circuits, " 1995 Proc. ofCICC, pp. 237240.
    • (1995) Proc. of CICC , pp. 237-240
    • Lokanathan, A.N.1    Brockman, J.B.2
  • 5
    • 0031707669 scopus 로고    scopus 로고
    • Statistical circuit characterization for deep-submicron CMOS designs
    • J. Chen, M. Orshansky, C. Hu, C.-P. Wan, "Statistical Circuit Characterization for Deep-Submicron CMOS Designs", 1998 Proc. ISSCC, pp.90-91.
    • 1998 Proc. ISSCC , pp. 90-91
    • Chen, J.1    Orshansky, M.2    Hu, C.3    Wan, C.-P.4
  • 6
    • 0030422227 scopus 로고    scopus 로고
    • E-T based statistical modeling and compact statistical circuit simulation methodologies
    • J. Chen, C. Hu, C.-P. Wan, P. Bendix, A. Kapoor, "E-T Based Statistical Modeling and Compact Statistical Circuit Simulation Methodologies, " 1996 Proc. of lEDM, pp. 635-638.
    • 1996 Proc. of LEDM , pp. 635-638
    • Chen, J.1    Hu, C.2    Wan, C.-P.3    Bendix, P.4    Kapoor, A.5
  • 8
    • 0029216206 scopus 로고    scopus 로고
    • Realistic worst-case spice file extraction using BSIM3
    • J. Chen, C. Hu, Z. Liu, P. Ko, "Realistic Worst-Case SPICE File Extraction Using BSIM3, " 1995 Proc. ofCICC, pp. 375-378.
    • 1995 Proc. OfCICC , pp. 375-378
    • Chen, J.1    Hu, C.2    Liu, Z.3    Ko, P.4
  • 9
    • 0003326780 scopus 로고
    • Statistical worst-case analysis for integrated circuits
    • S. R. Nassif, "Statistical Worst-Case Analysis for Integrated Circuits", Statistical Approach to VLSI, pp. 233-253, 1994.
    • (1994) Statistical Approach to VLSI , pp. 233-253
    • Nassif, S.R.1
  • 14
    • 85053122363 scopus 로고
    • MathSoft Inc
    • MathSoft Inc, S-Plus, 1994.
    • (1994) S-Plus


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.