Embedded at-speed testing schemes with low overhead for high speed digital circuits on multi-chip modules

Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon

Volumn , Issue , 1996, Pages 210-216

  Maier, Cliff A ^a   Greub, Hans ^a   Philhower, Bob ^a   Steidl, Sam ^a   Garg, Atul ^a   Ernest, Matthew ^a   Carlough, Steve ^a   Campbell, Pete ^a   McDonald, John F ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; DIGITAL INTEGRATED CIRCUITS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

HIGH FREQUENCY INPUT/OUTPUT SIGNALS; KNOWN GOOD DIE (KGD);

MULTICHIP MODULES;

EID: 0030410349     PISSN: 10632204     EISSN: None     Source Type: None    
DOI: 10.1109/ICISS.1996.552428     Document Type: Conference Paper

References (7)

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3. C. Maier A testing scheme for a sub-nanosecond access time static RAM 1994 Rensselaer Polytechnic Institute
4. C. Maunder Paving the way for testability standards IEEE Design and Test of Computers 3 4 65 1986
5. C. M. Maunder R. E. Tulloss Testability on TAP IEEE Spectrum 34 37 February 1992
6. B. Philhower Spartan RISC architecture for yield-limited technologies 1993 Rensselaer Polytechnic Institute
7. S. Weber JTAG finally becomes an off-the-shelf solution Electronics 65 9 13 10 August 1992