6 ns cycle 256 kb cache memory and memory management unit

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1993, Pages 88-89

  Heald, R A ^a   Holst, J C ^a  

^a Integraph Corp ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER CIRCUITS; PHYSICAL ADDRESSES;

ACCESS TIME; CONTROL LOGIC; DATA INPUT; PARALLEL AND PIPELINE; PSEUDOSTATIC; SENSE AMPLIFIER; TIME-SHARING;

MEMORY MANAGEMENT UNITS;

EID: 4243125298     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.1993.280072     Document Type: Conference Paper

References (4)

1. Proebsting, R., "Speed Enhancement Technique for CMOS Circuits", US. Patent No. 4985643.
2. Wendell, D., et al., "A 3.5 ns 2K x 9 Self-Timed SRAM", 1990 Symposium VLSI Circuits, pp. 49-50, June 1990.
3. Towler, F., et al., "A 128k 6.5nsAccess/5ns CycleMOS ECL Static RAM", ISSCC DIGEST OF TECHNICAL PAPERS, pp. 30-31, Feb. 1989.
4. Chappell, T., et al., "A2 nsCycle, 3, 8nsAccess512KBCMOSECL SRAM with a Fully Pipelined Architecture", IEEE J. Solid-state Circuits, vol. 26, pp. 1577-1585, 1991.