Investigation of stress induced leakage current in CMOS structures with ultra-thin gate dielectrics

Microelectronics Reliability

Volumn 37, Issue 10-11, 1997, Pages 1529-1532

  Jahan, C ^a   Barla, K ^a   Ghibaudo, G ^b  

^a ORANGE LABS   (France)

^b Grenoble INP Phelma   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; DEFECTS; DIELECTRIC MATERIALS; LEAKAGE CURRENTS; SEMICONDUCTING BORON; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE;

ELECTRON TRAPPING; STRESS INDUCED LEAKAGE CURRENT; ULTRA THIN GATE DIELECTRICS;

SEMICONDUCTOR DEVICE STRUCTURES;

EID: 0031249818     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(97)00101-7     Document Type: Article

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