Operation of a novel negative differential conductance transistor fabricated in a strained Si quantum well

IEEE Electron Device Letters

Volumn 18, Issue 9, 1997, Pages 432-434

  Koester, S J ^a   Ismail, K ^a   Lee, K Y ^a   Chu, J O ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRODES; HETEROJUNCTIONS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR QUANTUM WELLS; SILICON WAFERS;

CURRENT PEAK TO VALLEY RATIO; NEGATIVE DIFFERENTIAL CONDUCTANCE (NDC) TRANSISTORS;

GATES (TRANSISTOR);

EID: 0031234974     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.622520     Document Type: Article

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