On line adaptive data compression chip using arithmetic codes

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1996, Pages 360-363

  Jou, Jer Min ^a   Kuang, Shiann Rong ^a   Chen, Yuh Lin ^a   Chiang, Chung Yuan ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); COMPUTER HARDWARE; DATA COMPRESSION; DIGITAL ARITHMETIC; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; ONLINE SYSTEMS; RECURSIVE FUNCTIONS; ROM; TABLE LOOKUP;

ADAPTIVE BINARY ARITHMETIC CODES; ADAPTIVE STATISTICAL MODELING; ASYNCHRONOUS INTERFACE CIRCUIT; CARRY OVER PROBLEM; DECOMPRESSION; DESIGN FOR TESTABILITY; HARDWARE RESOURCE; INPUT OUTPUT COMMUNICATION; ON LINE ADAPTIVE DATA COMPRESSION CHIP; SOURCE TERMINATION;

VLSI CIRCUITS;

EID: 0029705108     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)