Integration of modified plasma-enhanced chemical vapor deposited tetraethoxysilane intermetal dielectric and chemical-mechanical polishing processes for 0.35 μm IC device reliability improvement

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 36, Issue 9 A, 1997, Pages 5492-5497

  Wang, Ying Lang ^a   Tseng, Wei Tsu ^b   Feng, Ming Shiann ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

Author keywords

Chemical mechanical polishing (CMP); Device reliability; Hot carriers; Intermetal dielectrics; Moisture resistance; PE TEOS

Indexed keywords

CHEMICAL POLISHING; CHEMICAL VAPOR DEPOSITION; DIELECTRIC MATERIALS; HOT CARRIERS; RELIABILITY; SILANES;

CHEMICAL MECHANICAL POLISHING; INTERLEVEL DIELECTRICS (ILD); TETRAETHOXYSILANE;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0031222180     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.36.5492     Document Type: Article

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