A bit-level pipelined VLSI architecture for the running order algorithm

IEEE Transactions on Signal Processing

Volumn 45, Issue 8, 1997, Pages 2140-2144

  Chen, Chun Te ^a   Chen, Liang Gee ^a   Hsiao, Jue Hsuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; PIPELINE PROCESSING SYSTEMS;

BIT LEVEL OPERATION; RUNNING ORDER ALGORITHM;

VLSI CIRCUITS;

EID: 0031198689     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/78.611236     Document Type: Article

References (17)

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