High Sample Rate Array Architectures for Median Filters

IEEE Transactions on Signal Processing

Volumn 42, Issue 3, 1994, Pages 707-712

  Chakrabarti, Chaitali ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA REDUCTION; DIGITAL FILTERS; SPECTRUM ANALYSIS; VLSI CIRCUITS;

ARRAY ARCHITECTURES; FEEDBACK PATHS;

DIGITAL SIGNAL PROCESSING;

EID: 0028384057     PISSN: 1053587X     EISSN: 19410476     Source Type: Journal    
DOI: 10.1109/78.277872     Document Type: Article

References (11)

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