An advanced Ge preamorphization salicide technology for ultra-thin-film SOI CMOS devices

IEEE Electron Device Letters

Volumn 18, Issue 7, 1997, Pages 309-311

  Hsiao, Tommy C ^a   Liu, Ping ^a   Woo, Jason C S ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHIZATION; AMORPHOUS FILMS; ION IMPLANTATION; MOSFET DEVICES; SECONDARY ION MASS SPECTROMETRY; SEMICONDUCTING BORON; SEMICONDUCTING GERMANIUM; SILICON ON INSULATOR TECHNOLOGY; THIN FILM DEVICES; ULTRATHIN FILMS; VAPOR DEPOSITION;

GERMANIUM PREAMORPHIZATION SALICIDE TECHNOLOGY; SELF ALIGNED SILICIDES;

CMOS INTEGRATED CIRCUITS;

EID: 0031192158     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.596921     Document Type: Article

References (10)

1. T. C. Hsiao, N. A. Kistler, and J. C. S. Woo, "Modeling the 1-V characteristics of fully-depleted submicrometer SOI MOSFET's," IEEE Electron Device Lett., vol. 15, pp. 45-47, 1994.
2. T. Mogami, H. Wakabayashi, Y. Saito, T. Tatsumi, T. Matsuki, and T. Kunio, "Low-resistance self-aligned Ti-silicide technology for subquarter-micron CMOS devices," IEEE Trans. Electron Devices, vol. 43, pp. 932-939, 1996.
3. J. A. Kittl, Q.-Z. Hong, M. Rodder, D. A. Prinslow, and G. R. Misium, "A Ti salicide process for 0.10-μm gate length CMOS technology," in Symp. VLSI Tech. Dig., 1996, pp. 14-15.
4. L. T. Su, M. J. Sherony, H. Hu, J. E. Chung, and D. A. Antoniadis, "Optimization of series resistance in sub-0.2-μm SOI MOSFET's," IEEE Electron Device Lett., vol. 15, pp. 363-365, 1994.
5. J. Foerstner, J. Jones, M. Huang, B.-Y. Hwang, M. Racanelli, and J. Tsao, "Behavior of contact-silicided TFSOI gate-structures," in Proc. IEEE Int. SOI Conf., 1993, pp. 86-87.
6. Y. Yamaguchi, T. Nishimura, Y. Akasaka, and K. Fujibayashi, "Selfaligned suicide technology for ultrathin SIMOX MOSFET's," IEEE Trans. Electron Devices, vol. 39, pp. 1179-1183, 1992.
7. T. C. Hsiao, P. Liu, and J. Woo, "A novel salicide technology for thinfilm SOI MOSFET's using Ge preamorphization," in Proc. IEEE Int. SOI Conf., 1996, pp. 126-127.
8. M.-A. Nicolet and S. S. Lau, "Formation and characterization of transition-metal silicides," VLSI Electron. Microstruct. Sci., Vol. 6 - Material and Process Characterization, p. 330, 1983.
9. J. Chung, M.-C. Jeng, J. E. Moon, A. T. Wu, T. Y. Chan, P. K. Ko, and C. Hu, "Deep-submicrometer MOS device fabrication using a photoresist-ashing technique," IEEE Electron Device Lett., vol. 9, pp. 186-188, 1988.
10. M. Yoshimi, M. Terauchi, A. Murakoshi, M. Takahashi, K. Matsuzawa, N. Shigyo, and Y. Ushiku, "Technology trends of silicon-on-insulator - Its advantages and problems to be solved," in IEDM Tech. Dig., 1994, pp. 429-432.