Low-resistance self-aligned Ti-silicide technology for sub-quarter micron CMOS devices

IEEE Transactions on Electron Devices

Volumn 43, Issue 6, 1996, Pages 932-939

  Mogami, Tohru ^a   Wakabayashi, Hitoshi ^a   Saito, Yukishige ^a   Tatsumi, Toru ^a   Matsuki, Takeo ^a   Kunio, Takemitsu ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHIZATION; CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); ION IMPLANTATION; MOSFET DEVICES; SEMICONDUCTOR JUNCTIONS; THIN FILMS; TITANIUM COMPOUNDS;

SELECTIVE SILICON DEPOSITION; SILICON FILMS; SOURCE DRAIN REGIONS; TITANIUM SILICIDE TECHNOLOGY;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0030165657     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.502126     Document Type: Article

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