Formal verification made easy

IBM Journal of Research and Development

Volumn 41, Issue 4-5, 1997, Pages 567-575

  Schlipf, T ^a,b,c,f   Buechner, T ^a,b,d,e,f   Fritz, R ^a,g,h   Helms, M ^h   Koehl, J ^h  

^a IBM   (Germany)

^b UNIVERSITY OF KARLSRUHE   (Germany)

^c ROBERT BOSCH GMBH   (Germany)

^d UNIVERSITY OF STUTTGART   (Germany)

^e Institut fur Mikroelektronik Stuttgart   (Germany)

^f IEEE   (Germany)

^g Fachhochschule Offenburg   (Germany)

^h IEEE ^*

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; SEQUENTIAL MACHINES; STATE SPACE METHODS;

FORMAL VERIFICATION (FV);

FORMAL LOGIC;

EID: 0031177368     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.414.0567     Document Type: Article

References (14)

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12. K. Turner, Ed., Using Formal Description Techniques, John Wiley & Sons, Inc., New York, 1993.
13. E. Clarke, R. Enders, and T. Filkorn, "Exploiting Symmetry in Temporal Logic Model Checking," Formal Methods in System Design 9, 77-104 (1996).
14. C. Ip and D. Dill, "Better Verification Through Symmetry," Formal Methods in System Design 9, 41-75 (1996).