The role of two-cycle simulation in the S/390 verification process

IBM Journal of Research and Development

Volumn 41, Issue 4-5, 1997, Pages 593-599

  Van Huben, Gary A ^a,b  

^a IBM   (United States)

^b CLARKSON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BOOLEAN FUNCTIONS; COMPUTER SIMULATION; ERROR CORRECTION; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; TIMING CIRCUITS;

ARRAY BUILT IN SELF TEST (ABIST); LEVEL SENSITIVE SCAN DESIGN (LSSD) RINGS; LOGIC BUILT IN SELF TEST (LBIST); TWO CYCLE SIMULATION;

COMPUTER AIDED LOGIC DESIGN;

EID: 0031176431     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.414.0593     Document Type: Article

References (2)

1. "VHSIC Hardware Description Language," IEEE Standard 1076, IEEE Standards Board, 345 E. 47th St., New York, NY 10017, 1994.
2. K. L. Shepard, S. M. Carey, E. K. Cho, B. W. Curran, R. F. Hatch, D. E. Huffman, S. A. McCabe, G. A. Northrop, and R. Seigler, "Design Methodology for the S/390 Parallel Enterprise Server G4 Microprocessor," IBM J. Res. Develop. 41, 515-547 (1997, this issue).