Clock skew minimization during fpga placement

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 4, 1997, Pages 376-385

  Zhu, Kai ^a  

^a Actel Corp   (United States)

Author keywords

Clock skew; FPGA; Placement

Indexed keywords

ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; LOGIC GATES; LOGIC PROGRAMMING; TREES (MATHEMATICS);

CLOCK SKEW; FIELD PROGRAMMABLE GATE ARRAY (FPGA);

LOGIC CIRCUITS;

EID: 0031124810     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.602474     Document Type: Article

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