KGPMIN: An efficient multilevel multioutput and-OR-XOR minimizer

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 3, 1997, Pages 257-265

  Chattopadhyay, Santanu ^a   Roy, Sumit ^c   Chaudhuri, Parimal Pal ^b  

^a INDIAN INSTITUTE OF ENGINEERING SCIENCE AND TECHNOLOGY   (India)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

AND OR XOR; Generalized rm; KGPMIN; KGPXORMIN; Literal count; Minimizer; Reed muller (rm)

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; ELECTRIC NETWORK SYNTHESIS; LOGIC GATES;

MULTILEVEL MINIMIZERS; REED MULLER (RM) MINIMIZATION;

COMBINATORIAL CIRCUITS;

EID: 0031094386     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.594831     Document Type: Article

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