Optimal equivalent circuits for interconnect delay calculations using moments

European Design Automation Conference - Proceedings

Volumn , Issue , 1994, Pages 164-169

  Kahng, Andrew B ^a   Muddu, Sudhakar ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC CONNECTORS; ELECTRIC NETWORK TOPOLOGY; EQUIVALENT CIRCUITS; MATHEMATICAL MODELS; SUBROUTINES; TRANSFER FUNCTIONS; TRANSMISSION LINE THEORY; TREES (MATHEMATICS); VLSI CIRCUITS;

INTERCONNECT DELAY CALCULATIONS; MOMENT MATCHING;

DELAY CIRCUITS;

EID: 0028712018     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)