Clock distribution design and verification for PowerPC* microprocessors

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1995, Pages 58-61

  Ganguly, Shantanu ^a   Hojat, Shervin ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; MICROPROCESSOR CHIPS;

CLOCK DISTRIBUTION; CLOCK SKEW; POWERPC MICROPROCESSOR;

TIMING CIRCUITS;

EID: 0029510044     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)