200 MHz 16 Mbit synchronous DRAM with block access mode

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1994, Pages 79-80

  Fujiwara, Atsushi ^a   Kikukawa, Hirohito ^a   Matsuyama, Kazuhiro ^a   Agata, Masashi ^a   Iwanari, Shunichi ^a   Fukumoto, Minako ^a   Yamada, Toshio ^a   Okada, Shozo ^a   Fujita, Tsutomu ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER GRAPHICS; DATA HANDLING; DATA TRANSFER; IMAGE PROCESSING; LOGIC DESIGN; STORAGE ALLOCATION (COMPUTER); TIMING CIRCUITS;

BLOCK ACCESS MODE; MOVING PICTURE IMAGE CODING EXPERT GROUP; SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORIES;

RANDOM ACCESS STORAGE;

EID: 0028603897     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)