Design and characterization of SiGe TFT devices and process using Stanford's test chip design environment

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 1997, Pages 143-145

  Kumar, M V ^a   Subramanian, V ^a   Saraswat, K C ^a   Plummer, J D ^a   Lukaszek, W ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; OPTIMIZATION; SEMICONDUCTING GERMANIUM; SEMICONDUCTING SILICON;

DIAGNOSTIC TEST MODULES;

THIN FILM TRANSISTORS;

EID: 0030702343     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICMTS.1997.589363     Document Type: Conference Paper

References (16)

1. I.-W. Wu Polycrystalline Silicon Thin Film Transistors for Liquid Crystal Displays Solid State Phenomena 37-38 553 564 1994
2. S. Jurichich T.-J. King K. Saraswat J. Mehlhaff Low Thermal Budget Polycrystalline Silicon-Germanium Thin-Film Transistors Fabricated by Rapid Thermal Processing Japanese Journal of Applied Physics 33 8b L1139 41 1994
3. V. Subramanian K. Saraswat H. Hovagimian J. Mehlhaff Optimization and modeling of silicon-germanium thin film transistors for AMLCD applications using a Plackett-Burman experimental design First International Workshop on Statistical Metrology First International Workshop on Statistical Metrology Honolulu HI 1996-June-9
4. M. V. Kumar W. Lukaszek J. D. Plummer A Test Structure Advisor and a Coupled,. Library-Based Test Structure Layout and Testing Environment Proceedings of the IEEE International Conference on Microelectronic Test Structures 201 206 Proceedings of the IEEE International Conference on Microelectronic Test Structures 1996-March
5. V. Subramanian K. Saraswat H. Hovagimian J. Mehlhaff Response surface optimization for high-performance solid-phase crystallized silicon-germanium thin film transistors SPIE Conference on Electronic Imaging SPIE Conference on Electronic Imaging San Jose CA 1997-February-8-14
6. N. Bhat P. P. Apte K. Saraswat Charge Trap Generation in LPCVD Oxides Under High Field Stressing IEEE Transactions on Electron Devices 43 4 554 560 1996
7. A. Slaoui C. Deng S. Talwar J. Kramer T. W. Sigmon Fabrication and doping of poly-SiGe using excimer laser processing Applied Physics, A (Solids and Surfaces) A59 2 203 207 1994
8. W. T. Wong J. Y.-C. Pan J. D. Plummer A Virtual Factory-Based Environment for Semiconductor Device Development Proceedings of IEEE/SEMI International Semiconductor Manufacturing Science Symposium 117 123 Proceedings of IEEE/SEMI International Semiconductor Manufacturing Science Symposium 1992-June
9. M. Koyaaagi Y. Baba K. Hata I.-W. Wu A. G. Lewis M. Fuse R. Bruce The Charge-Pumping Technique for Grain Boundary Trap Evaluation in Polysilicon TFTs IEEE Electron Device Letters 13 3 152 154 1992
10. Y. Sato K. Anzai F. Tadoroko Dose perturbation by wafer charging during ion implantation IEEE Transactions on Semiconductor Manufacturing 5 4 329 336 1992
11. J. E. Fair Rapid thermal processing for active matrix devices Solid State Technology 35 8 47 52 1992
12. T.-J. King J. P. McVittie K. C. Saraswat J. R. Pfiester Electrical properties of heavily doped polycrystalline silicon-germanium films IEEE Transactions on Electron Devices 41 2 228 232 1994
13. D. S. Holbrook Micropatterning for AMLCD fabrication SID International Symposium Digest of Technical Papers SID International Symposium Digest of Technical Papers 1994
14. SAMPLE User Guide 1 June 1991 UC-Berkeley Electronics Research Lab
15. N. Bhat A. Wang K. C. Saraswat Rapid Thermal Anneal of Gate Oxide for Low-Thermal-Budget TFTs SID International Symposium Digest of Technical Papers SID International Symposium Digest of Technical Papers 1996
16. A. W. Wang N. Bhat K. C. Saraswat TMCTS for gate dielectric in thin film transistors Spring Meeting of the Materials Research Society Spring Meeting of the Materials Research Society San Francisco CA 1996-April-11