A fault simulation method for crosstalk faults in synchronous sequential circuits

IEICE Transactions on Information and Systems

Volumn E80-D, Issue 1, 1997, Pages 38-43

  Itazakp, Noriyoshi ^a   Idomoto, Yasutaka ^a   Kinoshita, Kozo ^a  

^a OSAKA UNIVERSITY   (Japan)

Author keywords

Crosstalk fault; Fault simulation; Sequential circuit; Test

Indexed keywords

COMPUTER SIMULATION; CROSSTALK; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUIT TESTING; LOGIC GATES; VLSI CIRCUITS;

FAULT SIMULATION METHOD;

SEQUENTIAL CIRCUITS;

EID: 0030683769     PISSN: 09168532     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (3)

1. A.Rubio, N.Itazaki, X.Xu, and K.Kinoshita, "An approach to the analysis and detection of crosstalk faults in digital VLSI circuits," IEEE Trans, on CAD, vol.13, no.3, pp.387-395, March 1994.
2. R.Anglada and A.Rubio, "An approach to crosstalk effect analysis and avoidance techniques in digital CMOS VLSI circuits," Int.'l J. of Electronics, vol.6, no.5, pp. -17, 1988.
3. F.Brglez, D.Bryan, and K.Kozminski, "Combinational profiles of sequential benchmark circuits," Proc. Int.'l Sympo. on Circuits and Systems, pp.1929-1934, 1989.