Mixed sensing architecture for 64 Mbit 16-level-cell non-volatile memories

Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon

Volumn , Issue , 1996, Pages 133-140

  Calligaro, C ^a   Manstretta, A ^a   Rolandi, P ^a   Torelli, G ^a  

^a UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AMPLIFIERS (ELECTRONIC); SEMICONDUCTOR STORAGE; VOLTAGE DISTRIBUTION MEASUREMENT;

DICHOTOMIC ALGORITHM; ERASABLE PROGRAMMABLE READ ONLY MEMORY (EPROM); MULTILEVEL NONVOLATILE MEMORIES;

PROM;

EID: 0030422128     PISSN: 10632204     EISSN: None     Source Type: None    
DOI: 10.1109/ICISS.1996.552420     Document Type: Conference Paper

References (7)

1. M. Bauer A Multi-Level-Cell 32Mb Flash Memory Proc. IEEE Int. Solid-State Circuits Conf 132 133 Proc. IEEE Int. Solid-State Circuits Conf 1995
2. T. S. Jung A 3.3V 128Mb Multi-Level NAND Flash Memory for Mass Storage Applications Proc. IEEE Int. Solid-State Circuits Conf. 32 33 Proc. IEEE Int. Solid-State Circuits Conf. 1996
3. M. Ohkawa A 98mm2 3.3V Flash Memory with FN-NOR Type 4-level Cell Proc. IEEE Int. Solid-State Circuits Conf. 36 37 Proc. IEEE Int. Solid-State Circuits Conf. 1996
4. C. de Graaf P. Young D. Hulsbos Feasibility of multilevel storage in Flash EEPROM cells Proc. IEEE ESSDERC 213 216 Proc. IEEE ESSDERC 1995
5. T. Blyth S. Khan R. Simko A Non-Volatile Analog Storage Device Using EEPROM Technology Proc. IEEE Int. Solid-State Circuits Conf. 192 195 Proc. IEEE Int. Solid-State Circuits Conf. 1991
6. B. Donoghue P. Holly K. Ilgenstein A 256K HCMOS ROM Using a Four-State Cell Approach IEEE J. Solid-State Circuits SC-20 2 598 602 Apr. 1985
7. A. Bleiker H. Melchior A Four-State EEPROM Using Floating-Gate Memory Cells IEEE J. Solid-State Circuits SC-22 3 460 463 July 1987