MCM/IC timing-driven placement algorithm featuring explicit design space exploration

Proceedings of the IEEE Multi-Chip Module Conference

Volumn , Issue , 1996, Pages 170-175

  Esbensen, Henrik ^a   Kuh, Ernest S ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; COMPUTER AIDED DESIGN; CONSTRAINT THEORY; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; MULTICHIP MODULES; OPTIMIZATION; SIMULATED ANNEALING;

BUILDING BLOCK PLACEMENT; DESIGN SPACE EXPLORATION; ELMORE DELAY; MAXIMUM PATH DELAY; TIMING DRIVEN PLACEMENT ALGORITHM;

GENETIC ALGORITHMS;

EID: 0029780152     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)