Latency exploitation in circuit simulation by sparse matrix techniques

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1988, Pages 623-626

  van Eijndhoven, J T J ^a   van Stiphout, M T ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL TECHNIQUES--MATRIX ALGEBRA;

FINE-GRAINED LATENCY USE; PIECEWISE LINEAR CIRCUIT SIMULATOR; SPARSE MATRIX TECHNIQUES;

INTEGRATED CIRCUITS;

EID: 0024124850     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)