Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition

IEEE Transactions on Computers

Volumn 39, Issue 11, 1990, Pages 1359-1368

  Chakrabarti, Chaitali ^a   JáJá, Joseph ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

Architecture; bit serial; discrete cosine transform; discrete Hartley transform (DHT); prime factor decomposition; systolic; VLSI

Indexed keywords

MATHEMATICAL TRANSFORMATIONS;

DISCRETE COSINE TRANSFORMS; DISCRETE HARTLEY TRANSFORMS; PRIME FACTOR DECOMPOSITION; SYSTOLIC ARCHITECTURES;

COMPUTER ARCHITECTURE;

EID: 0025517054     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.61045     Document Type: Article

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