A weighted random pattern test generation system

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 8, 1996, Pages 1020-1025

  Kapur, Rohit ^a   Paul, Srinivas ^a   Snethen, Thomas J ^a   Williams, T W ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; COMPUTER AIDED LOGIC DESIGN; ERROR DETECTION; FAILURE ANALYSIS; PROBABILITY; RANDOM PROCESSES; VECTORS;

FAULT COVERAGE; WEIGHT GENERATION ALGORITHMS; WEIGHTED RANDOM PATTERN TESTING;

LOGIC CIRCUITS;

EID: 0030216624     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.511581     Document Type: Article

References (19)

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