Testing VLSI chips with weighted random patterns

Volumn , Issue , 1989, Pages 149-154

  Waicukauski, John A ^a   Motika, Franco ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE--TESTING; INTEGRATED CIRCUIT TESTING--COMPUTER AIDED ANALYSIS;

LEVEL-SENSITIVE SCAN DESIGN; TEST GENERATION; VLSI TESTING; WEIGHTED RANDOM PATTERNS;

INTEGRATED CIRCUITS, VLSI;

EID: 0024886109     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)