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Volumn 1, Issue , 1993, Pages 90-93
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New LSI Architecture for ultra-high-speed error correction and its application to the majority decoding LSI for (1057,813) code
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Author keywords
[No Author keywords available]
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Indexed keywords
DECODING;
ERROR CORRECTION;
LSI CIRCUITS;
CMOS TECHNOLOGY;
CORRECTION METHOD;
DECODING CIRCUITS;
DIFFERENCE-SET CYCLIC;
ITS APPLICATIONS;
LSI ARCHITECTURE;
PIPELINE ARCHITECTURE;
ULTRA HIGH SPEED;
MEMORY ARCHITECTURE;
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EID: 5844343134
PISSN: 19308833
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (4)
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References (7)
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