High-Speed Parallel Viterbi Decoding: Algorithm and VLSI-Architecture

IEEE Communications Magazine

Volumn 29, Issue 5, 1991, Pages 46-55

  Fettweis, Gerhard ^a   Meyr, Heinrich ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CODES, SYMBOLIC--DECODING; COMPUTER PROGRAMMING--ALGORITHMS; COMPUTER SYSTEMS, DIGITAL--PARALLEL PROCESSING;

ALGORITHM LEVEL PARALLELIZATION; BIT LEVEL PARALLELIZATION; HIGH SPEED VITERBI DECODERS; PIPELINE INTERLEAVING; VITERBI ALGORITHM; WORD LEVEL PARALLELIZATION;

SIGNAL PROCESSING;

EID: 0026153976     PISSN: 01636804     EISSN: None     Source Type: Journal    
DOI: 10.1109/35.79382     Document Type: Article

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