A scheme of pll with finite impulse responses

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 43, Issue 4, 1996, Pages 340-343

  Kobayashi, Fuminori ^a   Haratsu, Masayuki ^a  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; CONTROL EQUIPMENT; DIGITAL CONTROL SYSTEMS; FREQUENCY RESPONSE; LOGIC GATES; PHASE COMPARATORS; VARIABLE FREQUENCY OSCILLATORS;

DIGITAL CONTROLLER; FIELD PROGRAMMABLE GATE ARRAYS; FINITE IMPULSES RESPONSE; OVERSHOOTS; TIME OPTIMAL OPERATION;

PHASE LOCKED LOOPS;

EID: 0030129449     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.488815     Document Type: Article

References (5)

1. R. E. Best, Phase-Locked Loops, 2nd ed. New York: McGraw-Hill. 1993.
2. A. W. Moore, "Phase-locked loops for motor speed control," IEEE Spectrum, vol. 10, pp. 61-67, Apr. 1973.
3. J. Tal, "Speed control by phase-locked servo systems-New possibilities and limitations," IEEE Trans. Ind. Electron. Comr. Inslrum., vol. IECI 24, pp. 118-125, Feb. 1977.
4. F. M. Gardner. "Charge-pump phase-lock loops," IEEE Trans. Commun., vol. COM-28, pp. 717-718, Apr. 1980.
5. F. Kobayashi el J., "High-speed PLL and frequency synthesizer for low frequencies," IEEE Trans. Circuit Syst., vol. CAS-31, pp. 847-852, Oct. 1984.