High-Speed PLL and Frequency Synthesizer for Low Frequencies

IEEE Transactions on Circuits and Systems

Volumn 31, Issue 10, 1984, Pages 847-852

  Kobayashi, Fuminori ^a   Sakamoto, Yasuhiko ^b   Nakano, Michio ^b  

^a NAGAOKA UNIVERSITY OF TECHNOLOGY   (Japan)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

PHASE LOCKED LOOPS;

HIGH-SPEED PLL; LOW FREQUENCIES;

FREQUENCY SYNTHESIZERS;

EID: 0021515287     PISSN: 00984094     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCS.1984.1085434     Document Type: Article

References (9)

1. F. M. Gardner, Phase-Lock Techniques, 2nd ed., New York: Wiley, 1979.
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3. G. T. Volpe, “A phase-locked loop control system for a synchronous motor,” IEEE Trans. Automat. Contr., vol. AC-15, pp. 88–95, Feb. 1970.
4. A. W. Moore, “ Phase-locked loops for motor speed control,” IEEE Spectrum, vol. 10, pp. 61–67, Apr. 1973.
5. J. Tal, “Speed control by phase-locked servo systems—New possibilities and limitations,” IEEE Trans. Ind. Electron. Contr. Instrum., vol. IECI-24, pp. 118–125, Feb. 1977.
6. F. M. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Commun., vol. COM-28, pp. 1849–1858, Nov. 1980.
7. J. I. Brown, “A digital phase and frequency-sensitive detector,” Proc. IEEE, vol. 59, pp. 717–718, Apr. 1971.
8. B. C. Kuo, Digital Control Systems. New York: Holt, Rinehart & Winston, 1980, ch. 10.
9. M. Nakano et al., “Measurement of position for the centroid of a plane figure using a video camera,” IEEE Trans. Ind. Electron. Contr. Instrum., vol. IECI-27, pp. 62–67, May 1980.