Processing architectures for smart pixel systems

IEEE Journal on Selected Topics in Quantum Electronics

Volumn 2, Issue 1, 1996, Pages 24-33

  Wills, D Scott ^a,b,c,d   Baker Jr , James M ^b,c,e,f   Cat, Huy H ^b,c,g   Chai, Sek M ^b,c,h   Codrescu, Lucian ^b   Cruz Rivera, José ^b   Eble, John C ^b   Gentile, Antonio ^b   Hopper, Michael A ^b   Lacy, W Stephen ^b   Lôpez Lagunas, Abelardo ^a,b   May, Phil ^b   Smith, Scott ^b   Taha, Tarek ^b  

^a IEEE

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^d MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^e VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

^f VLSI Architectures Group

^g UNIVERSITY OF CENTRAL FLORIDA   (United States)

^h Georgia Tech

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CHARGE COUPLED DEVICES; MICROPROCESSOR CHIPS; OPTOELECTRONIC DEVICES;

SMART PIXELS; VIDEOPUTER SYSTEMS;

IMAGE PROCESSING;

EID: 0030114133     PISSN: 1077260X     EISSN: None     Source Type: Journal    
DOI: 10.1109/2944.541872     Document Type: Article

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