A 300-MHz 4-Mb Wave-Pipeline CMOS SRAM Using a Multiphase PLL

IEEE Journal of Solid-State Circuits

Volumn 30, Issue 11, 1995, Pages 1189-1195

  Toyoshima, Hiroshi ^a   Ohki, Nagatoshi ^a   Ishida, Hiroshi ^a   Yamanaka, Toshiaki ^a   Nagano, Takahiro ^a   Nishida, Takashi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; INTEGRATED CIRCUIT MANUFACTURE; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; PIPELINE PROCESSING SYSTEMS;

ADDRESS BUFFER; CURRENT SENSE AMPLIFIER; DATA PATHS PROPAGATION; DYNAMIC DECODERS; MULTIPHASE ACTIVE PULSE CONTROL; WAVE PIPELINE CMOS STATIC RANDOM ACCESS MEMORY;

RANDOM ACCESS STORAGE;

EID: 0029405188     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.475706     Document Type: Article

References (7)

1. K. Nakamura et al., “A 220 MHz pipelined 16 Mb BiCMOS SRAM with PLL proportional self-timing generator,” in ISSCC '94, Dig. Tech. Papers, p. 258.
2. T. Chappell et al., “A 2 ns cycle, 4 ns-access 512 kb CMOS ECL SRAM,” in ISSCC '91, Dig. Tech. Papers, p. 50.
3. A. Fujiwara et al., “A 200 MHz 16 M bit synchronous DRAM with block access mode,” in VLSI Circuits Symp. '94, Dig. Tech. Papers, p. 79.
4. J. G. Maneatis et al., “Precise delay generation using coupled oscillators,” in ISSCC '93, Dig. Tech. Papers, pp. 118–119.
5. K. Ishibashi et al., “A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers,” in '94 VLSI Circuits Symp., Dig. Tech. Papers, p. 107.
6. A. Sekiyama et al., “A 1-V operating 256-Kbit full CMOS SRAM,” in '90 VLSI Circuits Symp., Dig. Tech. Papers, p. 53.
7. M. Minami et al., “A 6.93-µm2 n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits,” in '94 VLSI Tech. Symp., Dig. Tech. Papers, p. 13.