High Speed Submicron BiCMOS Memory

IEEE Transactions on Electron Devices

Volumn 42, Issue 3, 1995, Pages 497-505

  Takada, Masahide ^a   Nakamura, Kazuyuki ^a   Yamazaki, Tohru ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); LOGIC GATES; RELIABILITY; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR STORAGE;

BICMOS MEMORY; POLYSILICON EMITTER STRUCTURES; PROCESS COMPLEXITY;

BIPOLAR INTEGRATED CIRCUITS;

EID: 0029271518     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.368046     Document Type: Article

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