A stacked emitter polysilicon (STEP) bipolar technology for 16Mb BiCMOS SRAMs

Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting

Volumn 1992-October, Issue , 1992, Pages 100-103

  Suzuki, H ^a   Nishigori, T ^a   Yamazaki, T ^a   Nakamura, K ^b   Oguri, T ^b   Atsumo, T ^b   Takada, M ^b   Ikemoto, A ^c  

^a VLSI Development Division ^*  (Japan)

^b Microelectronics Research Laboratories ^*  (Japan)

^c NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BICMOS TECHNOLOGY; POLYCRYSTALLINE MATERIALS; POLYSILICON; SILICIDES; STATIC RANDOM ACCESS STORAGE;

BI-CMOS; BIPOLAR TECHNOLOGY; CELL OPERATION; ELECTRODE STRUCTURE; GROUND LINES; HIGHLY STABLES; LOAD CELLS; POLYSILICON LAYERS;

THIN FILM TRANSISTORS;

EID: 84930093405     PISSN: 10889299     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BIPOL.1992.274074     Document Type: Conference Paper

References (4)

1. T. C. Male et al., IEDM Tech. Dig., P.481,1990
2. P. Ashbum, BCTM Tech. Dig., P.90,1989
3. J. N. Burghartz et al., Symp. on VLSI Technology, P.55, 1990
4. H. Ohkubo et al., IEDM Tech. Dig., P.481, 1991