Application of Multithreshold Elements in the Realization of Many-Valued Logic Networks

IEEE Transactions on Computers

Volumn C-23, Issue 11, 1974, Pages 1194-1198

  Druzeta, A ^a   Vranesic, Z G ^a   Sedra, A S ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

logic design; many valued logic; multithreshold elements; storate circuits; Switching systems

Indexed keywords

LOGIC DESIGN;

EID: 0016129398     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/T-C.1974.223829     Document Type: Article

References (8)

1. D. Hampel, “Multifunction threshold gate,” IEEE Trans. Comput., vol. COM-22, pp. 197–203, Feb. 1973.
2. D. Hampel and R. O. Winder, “Threshold logic,” IEEE Spectrum, vol. 8, pp. 32–39, May 1971.
3. D. R. Haring, “Multi-threshold building blocks,” IEEE Trans. Electron. Comput., vol. EC-15, pp. 662–663, Aug. 1966.
4. A. Druzeta, A. S. Sedra, and Z. G. Vranesic. “Integratable multi-threshold logic circuits,” to be published.
5. K. C. Smith, Z. G. Vranesic, and L. Janczewski, “Circuit implementations of multivalued logic,” in Proc. 1971 Symposium on Theory and Applications of Multiple-Valued Logic System, Buffalo, N. Y., May 1971, pp. 133–139.
6. K. A. EI Ayat and Z. G. Vranesic, “Application of multi-valued cyclic codes,” in Proc. 1971 Symposium on Theory and Applications of Multiple-Valued Logic Design, Buffalo, N. Y., May 1971, pp. 7–12.
7. Z. G. Vranesic and V. C. Hamacher, “Ternary logic in parallel multipliers,” Comput. J., vol. 15, pp. 254–258, Nov. 1972.
8. I. T. Ho and T. C. Chen, “Multiple addition by residue threshold functions and their representation by array logic,” IEEE Trans. Comput., vol. C-22, pp. 762–767, Aug. 1973.