A high-performance 0.5-μm BiCMOS technology with 3.3-V CMOS devices

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1990, Pages 89-90

  Johnson, E D ^a   Hook, T B ^a   Bertsch, J E ^a   Taur, Y ^b   Chen, C L ^b   Shin, H J ^b   Ramaswamy, S ^a   Edenfeld, A ^a   Alcorn, C ^a  

^a IBM   (United States)

^b IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BICMOS CIRCUITS; BIPOLAR DEVICE; CHANNEL LENGTH; CMOS COMPATIBLE; CMOS DEVICES; HEAT CYCLE; N-P-N TRANSISTORS; PERFORMANCE DEGRADATION; PERFORMANCE GAIN; POWER SUPPLY VOLTAGE; RELIABLE OPERATION;

CUTOFF FREQUENCY; POLYSILICON; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICES, MOS; TRANSISTORS, BIPOLAR;

BICMOS TECHNOLOGY; INTEGRATED CIRCUITS, CMOS;

BICMOS; CMOS DEVICES; DIGEST OF PAPER; NPN TRANSISTORS; POLYSILICON;

EID: 0025594077     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.1990.111022     Document Type: Conference Paper

References (3)

1. L. K. Wang et al, "0.5-μm Gate Technology Using E-Beam/Optical Mix Lithography," 1986 Symposium on VLSI Technology, p. 13.
2. C. L. Chen, "Level Shifted 0.5-μm BICMOS Circuits," to be presented at the 1990 International Solid-state Circuits Conference (ISSCC).
3. H. J. Shin et al, "Full-Swing Complementary BiCMOS Logic Circuits," 1989 Bipolar Circuits and Technology Meeting.