Level-Shifted 0.5-μm BiCMOS Circuits

IEEE Journal of Solid-State Circuits

Volumn 25, Issue 5, 1990, Pages 1214-1216

  Chen, Chih Liang ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS, DIGITAL - CIRCUITS; INTEGRATED CIRCUITS, CMOS;

CMOS TECHNOLOGY;

SEMICONDUCTOR DEVICES, MOS;

EID: 0025505106     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.62144     Document Type: Article

References (5)

1. S. C. Lee and D. W. Schucker, “BiCMOS driver circuit,” U.S. Patent 4 616146, Oct. 7, 1986.
2. C. L. Chen, “BiCMOS driver circuit for high density CMOS logic circuits,” U.S. Patent 4897564, Jan. 30, 1990.
3. C. L. Chen, “Level-shifted and voltage-reduced 0.5 μm BiCMOS circuits,” in ISSCC Dig. Tech. Papers, 1990, 236–237.
4. E. Johnson et al., “A 0.5 μm CMOS-based BiCMOS technology,” in Proc. 1990 Symp. VLSI Technol. (Hawaii), June 1990, pp. 89–90.
5. Y. Kobayashi et al., “High performance LSI process technology: SST-CBiCMOS,” in IEDM Tech. Dig., 1988, pp. 760–763.