Experimental and simulation study of the effects of cosmic particles on CMOS/SOS RAMs

IEEE Transactions on Nuclear Science

Volumn 37, Issue 6, 1990, Pages 1855-1860

  Worley, E ^a,b   Williams, R ^a,c   Waskiewicz, A ^a,d   Groninger, J ^a,d  

^a Rockwell International   (United States)

^b WESTERN DIGITAL CORPORATION   (United States)

^c Digital Communications Division ^*  (United States)

^d Autonetics Strategic Systems Division ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COSMIC RAYS; DATA STORAGE, DIGITAL--RANDOM ACCESS; TRANSISTORS, BIPOLAR;

CMOS/SOS CIRCUITS;

INTEGRATED CIRCUITS, CMOS;

EID: 0025592884     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.101201     Document Type: Article

References (9)

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2. G. E. Davis et al, “Transient Radiation Effects in SOI Memories”, IEEE Transactions on Nuclear Science, Vol. NS-32, No. 6, p. 4439, Dec. (1985).
3. J. Rollins, “Single Event Upset in Silicon Integrated Circuits”, PhD Thesis, University of So. California, 1989.
4. M. L. Alles, “Characterization of Single Event Vulnerability of CMOS-SOI Transistors”, in GOMAC 1989 Digest of Papers, p. 397.
5. S. E. Kerns et al, “Model for CMOS/SOI Single-Event Event Vulnerability”, IEEE Transactions on Nuclear Science, Vol. NS-36, No. 6, p. 2305, Dec. (1989).
6. S. M. Sze, Physics of Semiconductor Devices, 2nd Edition, John Wiley and Sons, p. 150, (1981).
7. D. Kranzer, “Spatial Dependence of the Carrier Lifetime in Thin Films of Silicon on Sapphire”, Applied Physics Letters, Vol. 25, p. 103, (1974).
8. E. Worley et al, “Comparison of Electrical Properties of SOS and ISE SOI Transistors”, in 1989 IEEE SOS/SOI Technology Conference Proceedings, p. 39.
9. C. A. Armstrong et al, “Characterization of Negative Resistance and Bipolar Latchup in Thin Film SOI Transistors by Two-Dimensional Numerical Simulation”, in 1989 IEEE SOS/SOI Technology Conference Proceedings, p. 44.