Thermal Stress Analysis of a Multichip Package Design

IEEE Transactions on Components, Hybrids, and Manufacturing Technology

Volumn 12, Issue 4, 1989, Pages 663-672

  Darveaux, Robert ^a,b   Turlik, Iwona ^a,c   Hwang, Lih Tyng ^a   Reisman, Arnold ^a,d  

^a MCNC   (United States)

^b NORTH CAROLINA STATE UNIVERSITY   (United States)

^c Bell Northern Research   (United States)

^d UNIVERSITY OF NORTH CAROLINA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRONICS PACKAGING; MATHEMATICAL TECHNIQUES;

DIE ATTACHMENT; FLIP-CHIP SOLDER BONDING; GLOBAL BENDING; INTEGRATED-CIRCUIT INTERCONNECTIONS; MULTICHIP PACKAGE; THIN-FILM INTERCONNECTIONS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0024942858     PISSN: 01486411     EISSN: None     Source Type: Journal    
DOI: 10.1109/33.49031     Document Type: Article

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