Multivalued Integrated Injection Logic

IEEE Transactions on Computers

Volumn C-26, Issue 12, 1977, Pages 1233-1241

  Dao, T Tich ^a   Russell, Lewis K ^a   McCluskey, Edward J ^a,b  

^a Philips Signetics Company   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

Multilevel I2L; Multivalued logic; Post logic; Quaternary flip flops; Quaternary logic; Quaternary ROM; Radix 4 arithmetic; Threshold I2L

Indexed keywords

LOGIC CIRCUITS;

EID: 0017703890     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1977.1674784     Document Type: Article

References (9)

1. J. J. Amodei, R. O. Winder, D. Hampel, and T. R. Mayhew, “An integrated threshold gate,” in 1967 Proc. ISSCC, pp. 114–115.
2. T. T. Dao, “Threshold logic gate,” U.S. Patent 3 838 393, Sept. 24, 1974.
3. B. A. Wooley and C. R. Baugh, “On integrated m out of n circuit using threshold logic,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 297–306, Oct. 1974.
4. T. T. Dao and P. A. Tucci, “Threshold integrated injection logic,” Patent Appl. No. 591 400, June 30, 1975.
5. M. I. Elmasry, “Folded-collector integrated injection logic,” IEEE J. Solid-State Circuits, pp. 644–647, Oct. 1975.
6. T. T. Dao, L. K. Russell, D. R. Preedy, and E. J. McCluskey, “Multilevel I2L with threshold gates,” in ISSCC Tech. Dig., Feb. 1977, pp. 110–111.
7. Z. G. Vranesic and K. C. Smith, “Engineering aspects of multi-valued logic systems,” Computer, vol. 7, no. 9, pp. 34–41, Sept. 1974.
8. A. Druzeta and A. S. Sedra, “Multi-threshold circuits in the design of multi-stage storage elements,” in Proc. 1973 Int. Symp. on Multiple-Valued Logic, Toronto, May 1973, pp. 49–58.
9. T. Higuchi and M. Kameyama, “Ternary logic systems based on T -gate,” in Proc. 1975 Int. Symp. Multivalued Logic, pp. 290–304; also, Indiana Univ., Bloomington, IN, May 13–16, 1975, IEEE Catalog 75CH0959-7C.