A non-slicing floorplanning algorithm using corner block list topological representation

IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings

Volumn , Issue , 2000, Pages 833-836

  Hong, Xianlong ^a   Dong, Sheqin ^a   Huang, Gang ^a   Ma, Yuchun ^a   Cai, Yici ^a   Cheng, Chung Kuan ^b   Gu, Jun ^c  

^a TSINGHUA UNIVERSITY   (China)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; OPTIMIZATION; SIMULATED ANNEALING; TOPOLOGY; VLSI CIRCUITS;

CORNER BLOCK LIST (CBL); FLOORPLANNING ALGORITHMS; VLSI FLOORPLANS;

COMPUTER SCIENCE;

EID: 0012932076     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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5. P.N.Guo, C.K.Cheng, " An O-tree representation of non-slicing floorplan and its applications", in: ACM/IEEE Design Automation Conference, 1999.
6. Xianlong Hong et al, "Corner Block List: An Efficient Topological Representation of Non-slicing Floorplan. ICCAD'2000 in San Jose, California. U.S.A