Field–programmable logic devices with optical input–output

Applied Optics

Volumn 39, Issue 5, 2000, Pages 721-732

  Szymanski, Ted H ^a   Saint Laurent, Martin ^b   Tyan, Victor ^c   Au, Albert ^d   Supmonchai, Boonchuay ^d  

^a MCMASTER UNIVERSITY   (Canada)

^b INTEL CORPORATION   (United States)

^c NOKIA RESEARCH CENTER   (United States)

^d MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0010868682     PISSN: 1559128X     EISSN: 21553165     Source Type: Journal    
DOI: 10.1364/AO.39.000721     Document Type: Article

References (20)

1. T. H. Szymanski and H. S. Hinton, “Architecture of a field programmable smart pixel array,” in Optics in Computing (Institute of Physics, Bristol, UK, 1995), pp. 497-500.
2. S. S. Sherif, T. H. Szymanski, and H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the 1996IEEE/LEOS Summer Topical Meeting (Institute of Electrical and Electronics Engineers, New York, 1996), pp. 78-79.
3. S. S. Sherif, S. K. Griebel, A. Au, D. Hui, T. H. Szymanski, and H. S. Hinton, “Field-programmable smart-pixel arrays: design, VLSI implementation, and applications,” Appl. Opt. 38, 838-846 (1999).
4. J. Depreitere, H. Neefe, H. van Marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, and I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Berlin, 1994), pp. 352-360.
5. M. Ishikawa, “System architecture for integrating optoelectronic computing,” Optoelectron. Devices Technol. 9, 29-36 (1994).
6. D. Fey, B. Kasche, C. Burkert, and O. Tschache, “Specifications for a reconfigurable optoelectronic VLSI processor suitable for digital signal processing,” Appl. Opt. 37, 284-295 (1998).
7. L. Selavo, S. P. Levitan, and D. M. Chiarulli, “An optically reconfigurable field programmable gate array,” in Digest of the Topical Meeting on Optics in Computing (Optical Society of America, Washington, D.C., 1999), pp. 146-148.
8. J. Mumbru and D. Psaltis, “Optically programmable gate array,” in Digest of the Topical Meeting on Optics on Computing (Optical Society of America, Washington, D.C., 1999), pp. 153-155.
9. T. H. Szymanski, M. Saint-Laurent, V. Tyan, A. Au, and B. Supmonchai, “A field programmable gate array with optical I/O,” in Digest of the Topical Meeting on Optics in Computing (Optical Society of America, Washington, D.C., 1999), pp. 149-152.
10. M. Leeser, W. Meleis, M. Vai, S. Chiricescu, and P. Zavracky, “Rothko: a three-dimensional FPGA,” IEEE Design Test. Comput. 15, 16-22 (1998).
11. A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, and L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128-130 (1999).
12. N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed. (Addison-Wesley, Reading, Mass., 1993), pp. 250-255.
13. N. H. E. Weste and K. Eshraghian Altera FPGA Data Book 1996 (Altera Corporation, 2610 Orchard Parkway, San Jose, Calif., 1995).
14. N. H. E. Weste and K. Eshraghian L-Edit Layout Editor Manual, Version 5 (Tanner Research, Inc., 2650 East Foothill Boulevard, Pasadena, Calif., 1995).
15. T. H. Szymanski and V. Tyan, “Error and flow control in terabit intelligent optical backplanes,” J. Select. Top. Quantum Electron. 5, 339-352 (1999).
16. M. Saint-Laurent, “Software programmable logic array,” Undergraduate honors thesis (Department of Electrical and Computer Engineering, McGill University, Montreal, Quebec, Canada, 1997).
17. E. Karali, Digital Design Principles and Computer Architecture (Prentice-Hall, New York, 1997).
18. T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, and R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-p.m silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422-424 (1996).
19. T. M. Slagle and K. H. Wagner, “Optical smart-pixel-based Clos crossbar switch,” Appl. Opt. 36, 8336-8351 (1997).
20. J. Depreitere, H. van Marck, and J. Van Campenhout, “A quantitative analysis of the benefits of the use of area I/O pads in FPGA’s,” Microprocess. Microsys. 21, 89-97 (1997).