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Volumn 38, Issue 5, 1999, Pages 838-846

Field-programmable smart-pixel arrays: Design, VLSI implementation, and applications

Author keywords

[No Author keywords available]

Indexed keywords


EID: 0001064097     PISSN: 1559128X     EISSN: 21553165     Source Type: Journal    
DOI: 10.1364/AO.38.000838     Document Type: Article
Times cited : (35)

References (13)
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    • Field programmable smart pixel arrays for an intelligent optical backplane
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    • (1996) Proceedings of the Fourth Canadian Workshop on Field Programmable Devices , pp. 55-61
    • Szymanski, T.H.1
  • 4
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    • Design and implementation of a field programmable smart pixel array
    • Institute of Electrical and Electronics Engineers, New York
    • S. S. Sherif, T. H. Szymanski, and H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the 1996IEEE/LEOS Summer Topical Meeting (Institute of Electrical and Electronics Engineers, New York, 1996), pp. 78-79.
    • (1996) Proceedings of the 1996IEEE/LEOS Summer Topical Meeting , pp. 78-79
    • Sherif, S.S.1    Szymanski, T.H.2    Hinton, H.S.3
  • 5
    • 0041740481 scopus 로고    scopus 로고
    • Smart-pixel-based network interface chip
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  • 6
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    • D. Fey, B. Kasche, C. Burkert, and O. Tschache, “Specifications for a reconfigurable optoelectronic VLSI processor suit-able for digital signal processing,” Appl. Opt. 37, 284-295 (1998).
    • (1998) Appl. Opt. , vol.37 , pp. 284-295
    • Fey, D.1    Kasche, B.2    Burkert, C.3    Tschache, O.4
  • 7
    • 0028385158 scopus 로고
    • System architecture for integrating optoelectronic computing
    • M. Ishikawa, “System architecture for integrating optoelectronic computing,” Optoelectron. Devices Technol. 9, 29-36 (1994).
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    • Ishikawa, M.1
  • 10
    • 0001519087 scopus 로고    scopus 로고
    • A reconfigurable intelligent optical backplane for parallel computing and communications
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    • Szymanski, T.H.1    Hinton, H.S.2
  • 11
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  • 12
    • 0030100467 scopus 로고    scopus 로고
    • Analysis of a microchannel interconnect based on the clustering of smart-pixel-device windows
    • D. R. Rolston, B. Robertson, H. S. Hinton, and D. V. Plant, “Analysis of a microchannel interconnect based on the clustering of smart-pixel-device windows,” Appl. Opt. 35, 1220-1233 (1996).
    • (1996) Appl. Opt. , vol.35 , pp. 1220-1233
    • Rolston, D.R.1    Robertson, B.2    Hinton, H.S.3    Plant, D.V.4
  • 13
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    • Experimental performance of an ATM-based buffered hyperplane CMOS-SEED smart pixel array
    • R. T. Chen and P. S. Guilfoyle, eds., Proc. SPIE
    • S. K. Griebel, M. Richardson, K. E. Devenport, and H. S. Hinton, “Experimental performance of an ATM-based buffered hyperplane CMOS-SEED smart pixel array,” in Optoelectronic Interconnects and Packaging IV, R. T. Chen and P. S. Guilfoyle, eds., Proc. SPIE 3005, 254-256 (1997).
    • (1997) Optoelectronic Interconnects and Packaging IV , vol.3005 , pp. 254-256
    • Griebel, S.K.1    Richardson, M.2    Devenport, K.E.3    Hinton, H.S.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.