A low-voltage CMOS multiplier and its application to a 900 MHz RF downconversion mixer

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 2000, Pages 108-111

  Debono, C J ^a   Maloberti, F ^a   Micallef, J ^b  

^a UNIVERSITY OF PAVIA   (Italy)

^b UNIVERSITY OF MALTA   (Malta)

Author keywords

[No Author keywords available]

Indexed keywords

900 MHZ; ANALOG MULTIPLIERS; CMOS MULTIPLIERS; CMOS TECHNOLOGY; DOWNCONVERSION MIXER; LOCAL OSCILLATOR SIGNALS; LOW POWER; LOW-VOLTAGE; RF SIGNAL; SIMULATION RESULT; SPUR-FREE DYNAMIC RANGE; VOLTAGE FOLLOWER; VOLTAGE OUTPUT; VOLTAGE-TO-CURRENT CONVERTERS;

CMOS INTEGRATED CIRCUITS;

FREQUENCY MULTIPLYING CIRCUITS;

EID: 0009471752     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2000.911496     Document Type: Conference Paper

References (6)

1. J. Crols, M.S.J. Steyaert, "A 1.5 GHz Highly Linear CMOS Downconversion Mixer, " IEEE J. Solid-State Circuits, vol.30, pp. 736-742, July 1995.
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5. S. Hsiao, C. Wu, "A Parallel Structure for CMOS Four-Quadrant Analog Multipliers and its Application to a 2 GHz RF Downconversion Mixer", IEEE J. Solid-State Circuits, vol 33, pp. 859-869, June 1998.
6. C-H. Lin, M. Ismail, "A 1.8 V Low-Power CMOS High-Speed Four Quadrant Multiplier with Rail-to-Rail Differential Input, " Proc. of The 5th Int. Conference on Electronics, Circuits and Systems, vol.1, pp. 37-40, Sep. 1998.