Advanced self aligned SOI concepts for vertical MOS transistors with ultrashort channel lengths

European Solid-State Device Research Conference

Volumn , Issue , 1997, Pages 628-631

  Aeugle, Th ^a   Risch, L ^a   Rosner, W ^a   Schulz, Th ^a   Behammer, D ^b  

^a SIEMENS AG   (Germany)

^b DAIMLER AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL LENGTH; DEVICE SIMULATIONS; FULLY DEPLETED; HIGH SPEED; MOBILE COMMUNICATIONS; REDUCED PRESSURE; SELF-ALIGNED; ULTRASHORT CHANNELS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0343727714     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.1997.194507     Document Type: Conference Paper

References (4)

1. L. Risch et ak, Vertical MOS Transistors with 70rzm Channel Length Proceedings of ESSDERC, pp. 101-103, 1995
2. W. ROsier et al, Processing and Evaluation of Ultrashort Vertical MOS , GMM Technical Digest 97
3. S. M. Sze, Physics of Semiconductor Devices, pp 493-494, John Whiley & Sons, 1981
4. SILVACO InternationaL, ATIWNA & ATLAS simulation tools, Santa Clara, CA 94054, USA, 1996