Delay estimation and optimization of logic circuits: A survey

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 1997, Pages 25-30

  Fujita, Masahiro ^a   Murgai, Rajeev ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONFORMAL MAPPING; OPTIMIZATION; PARAMETER ESTIMATION;

DELAY ESTIMATION; LOGIC CIRCUITS DELAY;

COMBINATORIAL CIRCUITS;

EID: 0030706477     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)