On using ATPG vectors for BIST TPG

AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Volumn , Issue , 1999, Pages 359-362

  Asakawa, T ^a   Iwasaki, K ^a  

^a TOKYO METROPOLITAN UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0001763309     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APASIC.1999.824104     Document Type: Conference Paper

References (5)

1. H. Yokoyama, X. Wen, H. Tamamoto, "Random Pattern Testable Design with Partial Circuit Duplication, " Asian 'lest Symposium, pp. 353-358, 1997.
2. S. Wang and S. Gupta, "DS-LFSR: A New BIST TPG for Low Heat Dissipation, " International Test Conference, pp. 848-857, 1997.
3. S. Hellebrand, S. Tarnick, S. Venkataraman, B. Courtois, "Built-in Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Resisters, " IEEE Trans. Comput., Vol. 44, No. 2, pp. 223-233, Feb. 1995.
4. J. Savir, "On Chip Weighted Random Patterns, " Asian Test Symposium, pp. 344-352, 1997.
5. S. Kajihara, I. Pomeranz, K. Kinoshita, S. M. Reddy, "On Compacting Test Sets by Addition and Removal of Test Vectors, " VLSI Test Symposium, pp. 202-207, 1994.