Random pattern testable design with partial circuit duplication

Proceedings of the Asian Test Symposium

Volumn , Issue , 1997, Pages 353-358

  Yokoyama, Hiroshi ^a   Wen, Xiaoqing ^a   Tamamoto, Hideo ^a  

^a AKITA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT IN SELF TEST (BIST) SCHEME; PARTIAL CIRCUIT DUPLICATION;

COMBINATORIAL CIRCUITS; LOGIC GATES; RANDOM PROCESSES;

INTEGRATED CIRCUIT TESTING;

EID: 0031377880     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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